tap4 for free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800. for small orders, phone 408-737-7600 ext. 3468. _______________general description the mxd1005 silicon delay line offers five equally spaced taps with delays ranging from 12ns to 250ns and a nominal accuracy of ?ns or ?%, whichever is greater. relative to hybrid solutions, this device offers enhanced performance and higher reliability, and reduces overall cost. each tap can drive up to ten 74ls loads. the mxd1005 is available in multiple versions, each offering a different combination of delay times. it comes in the space-saving 8-pin ?ax package, as well as an 8-pin so or dip, allowing full compatibility with the ds1005 and other delay line products. ________________________applications clock synchronization digital systems ____________________________features ? improved second source to ds1005 ? available in space-saving 8-pin ?ax package ? 17ma supply current vs. dallas?40ma ? low cost ? delay tolerance of ?ns or ?%, whichever is greater ? ttl/cmos-compatible logic ? leading- and trailing-edge accuracy ? custom delays available mxd1005 5-tap silicon delay line ________________________________________________________________ maxim integrated products 1 tap3 tap5 gnd 1 2 8 7 v cc tap1 tap2 tap4 in dip/so/ m max top view 3 4 6 5 mxd1005 14 13 12 11 10 9 8 1 2 3 4 5 6 7 v cc n.c. tap1 n.c. tap2 n.c. n.c. in mxd1005 tap3 n.c. tap5 gnd tap4 n.c. dip _________________pin configurations _____part number and delay times 19-1309; rev 0; 10/97 part mxd1005c/d__ mxd1005pa__ mxd1005pd__ -40? to +85? -40? to +85? 0? to +70? temp. range pin-package dice* 8 plastic dip 14 plastic dip ______________ordering information * dice are tested at t a = +25?. note: to complete the ordering information, fill in the blank with the part number extension from the part number and delay times table to indicate the desired delay per output. mxd1005sa__ mxd1005se__ mxd1005ua__ -40? to +85? -40? to +85? -40? to +85? 8 so 16 narrow so 8 ?ax pin configurations continued at end of data sheet. 60 12 part number extension (mxd1005_ _ __) 75 15 125 100 20 25 175 150 30 35 250 200 40 50 24 30 40 50 60 70 80 100 36 45 60 75 90 105 120 150 48 60 80 100 120 140 160 200 delay (t phl , t plh ) per output (ns) 60 75 100 125 150 175 200 250 note: contact factory for characterization data. functional diagram appears at end of data sheet. tap1 tap2 tap3 tap4 tap5
mxd1005 5-t ap silicon delay line 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (v cc = +5.0v 5%, t a = -40 c to +85 c, unless otherwise noted. typical values are at t a = +25 c.) (note 1) timing characteristics (v cc = +5.0v 5%, t a = +25 c, unless otherwise noted.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. note 1: specifications to -40 c are guaranteed by design, not production tested. note 2: all voltages referenced to gnd. note 3: measured with outputs open. note 4: i cc is a function of frequency and tap5 delay. only an mxd1005_ _60 operating with a 40ns period and v cc = +5.25v will have a maximum i cc of 70ma. for example, an mxd1005_ _100 will not exceed 30ma. see supply current vs. input frequency graph in typical operating characteristics. note 5: guaranteed by design. note 6: pulse width and/or period specifications may be exceeded, but accuracy is application sensitive (i.e., layout, decoupling, etc. ). note 7: v cc = +5v at +25 c. typical delays are accurate on both rising and falling edges within 2ns or 3%. note 8: see test conditions section. note 9: the combination of temperature variations from +25 c to 0 c or +25 c to +70 c and voltage variation from 5.0v to 4.75v or 5.0v to 5.25v may produce an additional typical input-to-tap delay shift of 1.5ns or 4%, whichever is greater. note 10: all taps and outputs delays tend to vary unilaterally with temperature or supply variations. for example, if tap1 slows down, all other taps will also slow down; tap3 cannot be faster than tap2. v cc to gnd .............................................................. -0.5v to +6v all other pins .............................................. -0.5v to (v cc + 0.5v) short-circuit output current (1sec) .................................... 50ma continuous power dissipation (t a = +70 c) 8-pin plastic dip (derate 9.1mw/ c above +70 c) ...... 727mw 14-pin plastic dip (derate 10.0mw/ c above +70 c) .. 800mw 8-pin so (derate 5.9mw/ c above +70 c) .................. 471mw 16-pin narrow so (derate 8.7mw/ c above +70 c) .... 696mw 8-pin max (derate 4.1mw/ c above +70 c) ............. 330mw operating temperature range ........................... -40 c to +85 c storage temperature range ............................. -65 c to +160 c lead temperature (soldering, 10sec) ............................. +300 c (note 2) (note 2) (note 2) t a = +25 c (note 5) 0v v in v cc v cc = 5.25v, period = minimum (notes 3, 4) v cc = 4.75v, v oh = 4.0v v cc = 4.75v, v ol = 0.5v conditions v 0.8 v il input voltage low v 2.2 v ih v 4.75 5.00 5.25 v cc supply voltage input voltage high pf 5 10 c in input capacitance a -1 1 i l input leakage current ma 17 70 i cc active current ma -1 i oh output current high ma 12 i ol output current low units min typ max symbol parameter (notes 7?0) (notes 7?0) (note 6) (note 6) conditions ns see part number and delay times table t phl input-to-tap delay (trailing edge) ns see part number and delay times table t plh ns 40% of tap5 t plh t wi input pulse width input-to-tap delay (leading edge) ms 100 t pu power-up time ns 4(t wi ) period units min typ max symbol parameter
mxd1005 5-t ap silicon delay line _______________________________________________________________________________________ 3 __________________________________________ t ypical operating characteristics (v cc = +5v, t a = +25 c, unless otherwise noted.) -2.0 -1.0 -1.5 0 -0.5 1.5 1.0 0.5 2.0 -40 0 -20 20 40 60 80 100 mxd1005_ _75 percent change in delay vs. temperature mxd1005 toc1 temperature (?) % change in delay (tap2) t plh relative to nominal (+25?) t phl t phl t plh -2.0 -1.0 -1.5 0 -0.5 1.5 1.0 0.5 2.0 -40 0 -20 20 40 60 80 100 mxd1005_ _100 to mxd1005_ _200 percent change in delay vs. temperature mxd1005 toc2 temperature (?) % change in delay (tap2) t phl relative to nominal (+25?) t phl t plh t plh -2.0 -1.0 -1.5 0 -0.5 1.5 1.0 0.5 2.0 -40 0 -20 20 40 60 80 100 mxd1005_ _250 percent change in delay vs. temperature mxd1005 toc3 temperature (?) % change in delay (tap2) t phl relative to nominal (+25?) t plh t plh t phl 18 10 11 12 13 14 15 16 17 0.001 0.1 1 0.01 10 active current vs. frequency mxd1005 toc4 frequency (mhz) active current (ma) 50% duty cycle mxd1005_ _75 mxd1005_ _200
_______________ definitions of t er ms period: the time elapsed between the first pulse? leading edge and the following pulse? leading edge. pulse width (t wi ): the time elapsed on the pulse between the 1.5v level on the leading edge and the 1.5v level on the trailing edge, or vice-versa. input rise time (t rise ): the time elapsed between the 20% and 80% points on the input pulse? leading edge. input fall time (t fall ): the time elapsed between the 80% and 20% points on the input pulse? trailing edge. time delay, rising (t plh ): the time elapsed between the 1.5v level on the input pulse? leading edge and the corresponding output pulse? leading edge. time delay, falling (t phl ): the time elapsed between the 1.5v level on the input pulse? trailing edge and the corresponding output pulse? trailing edge. ____________________ t est conditions ambient temperature: +25 c 3 c supply voltage (v cc ): +5v 0.01v input pulse: high = 3.0v 0.1v low = 0.0v 0.1v source impedance: 50 max rise and fall times: 3.0ns max pulse width: 500ns max period: 1 s each output is loaded with a 74f04 input gate. delay is measured at the 1.5v level on the rising and falling edges. the time delay due to the 74f04 is subtracted from the measured delay. mxd1005 5-t ap silicon delay line 4 _______________________________________________________________________________________ ______________________________________________________________ pin description 1 1 signal input 14-pin dip function 8-pin dip/so/ max name 16-pin so 2 4 40% of specified maximum delay 4 1 in tap2 3 pin 6 80% of specified maximum delay 4 7 device ground 8 6 tap4 gnd 5 8 100% of maximum specified delay 6 10 60% of specified maximum delay 11 9 tap5 tap3 7 12 20% of specified maximum delay 8 14 power-supply input 16 13 tap1 v cc 2, 3, 5, 9, 11, 13 no connection. not internally connected. 2, 3, 5, 7, 10, 12, 14, 15 n.c. note: maximum delay is determined by the part number extension. see the part number and delay times table for more information.
__________ applications infor mation supply and temperature effects on delay variations in supply voltage may affect the mxd1005? fixed tap delays. supply voltages beyond the specified range may result with larger variations. the devices are internally compensated to reduce the effects of temper - ature variations. although these devices might vary with supply and temperature, the delays vary unilaterally, which suggests that tap3 can never be faster than tap2. capacitance and loading effects on delay the output load can affect the tap delays. larger capacitances tend to lengthen the rising and falling edges, thus increasing the tap delays. as the taps are loaded with other logic devices, the increased load will increase the tap delays. board layout considerations/decoupling the device should be driven with a source that can deliver the required current for proper operation. a 0.1 f ceramic bypassing capacitor could be used. the board should be designed to reduce stray capaci - tance. mxd1005 5-t ap silicon delay line _______________________________________________________________________________________ 5 v il v ih period t rise in out 0.6v 0.6v 2.4v 2.4v 1.5v 1.5v 1.5v 1.5v 1.5v t fall t wi t plh t phl 20% 50 w 0.1? v cc in (+5v) 20% time measurement unit tap1 tap2 tap3 tap4 tap5 74fo4 20% 20% 20% mxd1005 figure 1. timing diagram figure 2. test circuit
mxd1005 5-t ap silicon delay line 6 _______________________________________________________________________________________ _________________________________________________________ functional diagram ___________________ chip infor mation transistor count: 824 mxd1005 tap1 tap2 tap3 tap4 tap5 in 20% 20% 20% 20% 20% ____ pin configurations (continued) top view 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 in v cc n.c. n.c. tap1 n.c. tap3 n.c. tap5 mxd1005 so n.c. n.c. tap4 tap2 n.c. n.c. gnd
mxd1005 5-t ap silicon delay line _______________________________________________________________________________________ 7 ________________________________________________________ package infor mation 8lumaxd.eps
mxd1005 5-t ap silicon delay line maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 8 _____________________ maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 1997 maxim integrated products printed usa is a registered trademark of maxim integrated products. ___________________________________________ package infor mation (continued) soicn.eps
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